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Artesyn ARTM-831X Installation and Use (June 2014) manuali

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Artesyn ARTM-831X Installation and Use (June 2014) Manuale Utente (346 pagine)


Marchio: Artesyn | Categoria: Apparecchiature | Dimensione: 20.75 MB |

 

Indice

ARTM-831X

1

Trademarks

2

Contact Address

2

Contents

10

List of Tables

11

List of Figures

15

About this Manual

17

Abbreviations

18

Conventions

23

Summary of Changes

25

Introduction

27

1.2 Features

28

1.2.1 ARTM 8310_base

29

1.2.2 ARTM-831X_E1/T1

30

1.2.3 ARTM-831X_DS3/OC3

31

1.3 Standard Compliances

32

1.4 Mechanical Data

35

1.5 Ordering Information

35

1.6 Product Identification

36

Chapter 2

37

2.2.2 RTM Power Specification

39

2.3.1 Installing the RTM

42

2.3.2 Removing the RTM

44

Procedure

47

SFP Module Damage

48

2.4.2 Removing an SFP Module

49

Chapter 3

53

3.1 Mechanical Layout

53

3.2 Face Plate

54

3.2.1 LEDs and Interfaces

55

Figure 3-3 ARTM-8310 LEDs

56

3.2.2 Connectors

57

Functional Description

61

4.2 ARTM-831X Base Unit

66

4.2.1.1 SPI Interface

67

4.2.1.2 Ref Clock Selection

68

4.2.1.3 Register Description

68

4.2.3 10G Ethernet Interface

69

4.2.5 BITS Interfaces

70

4.2.6 OC3 option

70

4.2.6.1 SFP Overhead Signals

71

4.2.6.2 ESSI Signals

71

4.2.7.1 Temperature Sensors

73

4.3.1 TSI FPGA

75

4.3.1.2 Clock Selection

76

4.3.1.3 Local Bus

76

4.3.1.4 TSIP2SERDES Interface

76

. . . . . . .

76

4.3.2 TSI-Extender FPGA

77

4.3.2.2 Clock selection

78

4.3.2.3 Register Description

78

4.3.3.1 H-MVIP Interface

79

4.3.3.2 Local Bus

79

ATCA -Backplane

81

4.3.4 FRU Data

82

4.4.1 TSI FPGA

82

To base board via

83

4.4.1.4 Local Bus

84

4.4.1.6 Register Description

84

4.4.2 TSI-Extender FPGA

85

4.4.2.2 Clock selection

86

4.4.2.4 Register Description

87

4.4.3.1 SBI336 Interface

87

4.4.3.2 Local Bus

87

4.4.3.3 Line Side Interfaces

88

4.4.4 E1/T1 Framer-LIU

89

4.4.4.1 H-MVIP Interface

90

4.4.4.2 Local Bus

90

4.4.6 FRU data

93

5.2 Firmware architecture

96

5.4 Accessing SFP EEPROMs

98

5.5 Artesyn OEM Command Set

98

5.6 Patch Panel Detection

99

Module Management Controller

100

5.7 IPMI Hardware Watchdog

101

5.8 SFP I2C Selection

101

Chapter 6

103

6.1 FRU Information

103

6.2 Power Configuration

105

6.3 Sensor Data Records

105

6.3.2 SFP TXFAULT Sensors

106

Sensor Data Records

109

7.1 Sensor Data Records

109

Base ARTM FPGA

115

8.1.1 Unit Description

116

8.2 Signals

117

8.2.8 Telecom Clocks

120

8.2.9 Status Sonet SFP

120

8.2.10 Control Sonet SFP

121

8.2.12 GE Control Signals

123

8.2.13 Ethernet Clock Signals

123

8.2.14 BITS 1 Signals

124

8.2.15 BITS 2 Signals

125

8.2.16 Identification Signals

126

8.2.17 Debug LEDs

126

8.2.18 Spare Signals

126

8.2.19 Configuration Signals

127

8.3 Registers

128

8.3.1.4 SFP TXFAULT Status

133

8.3.1.5 SFP MOD_ABS Status

133

8.3.1.6 SFP TXDIS Control

134

8.3.1.7 10 GE Status Register

134

8.3.1.9 MMC Scratch Register

136

8.3.1.10 RTM Scratch Register

136

8.3.1.12 GE Control Register

137

8.3.1.14 Test Register

139

8.3.1.15 Other Status Signals

139

8.3.1.18 SFP MOD_ABS changed

141

8.3.1.20 10 GE Status changed

141

8.4 Reset Structure

151

8.5 Clocking Scheme

152

8.6 Logic Blocks

152

8.6.3.3 MMC I2C Forwarding

153

TSI FPGA

157

9.1.1 Unit Description

158

9.2 Device Specifics

160

9.3 TSI FPGA Signals Overview

162

9.4 Logic Blocks

163

9.4.2 GR8

165

9.4.8 PCIexpress Interface

167

9.4.11 SPI Expander Interface

169

9.4.12 Interrupt Controller

169

9.4.13 Debug LEDs

169

9.5 RTM FPGA HW/SW Interfaces

171

9.5.2.1 TSI Memory (TsiMem)

193

9.5.2.2 GR8 Memory (Gr8Mem)

195

(FrLiuSdBndRegs)

265

9.5.3 PCI Configuration Space

281

9.5.3.2 Detailed Description

282

9.6 TSI channel mapping

288

EXT FPGA

293

10.2 Device Specifics

294

10.3 Logic Blocks

295

Related Documentation

335

Safety Notes

337

Installation

338

Operation

339

Environment

339

SFP Modules

340

Sicherheitshinweise

341

Umweltschutz

344




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